1. Field of the Invention
The present invention relates to a synchronous communications multiplexer for connecting a plurality of synchronous communications lines to an MP (multi-purpose) bus of a host computer via an input output processor. In its basic form, the multiplexer is capable of handling bit protocols (BOP) and is capable of being upgraded to support byte-oriented protocols. The present invention supports full- or half-duplex data rates up to 19,200 baud. Total throughput, when operating with four ports (as an example), is in the range of 76.8 kbits/sec. A special mode of operation (unisync) allows operating a single port at 56 kbits/sec., full duplex.
2. Description of the Prior Art
Up to this point, prior art practitioners have not developed a communications multiplexer which is capable of multi-protocol operation as described above with respect to the present invention.
One communications controller of the prior art is disclosed in U.S. Pat. No. 4,079,452--Larson et al. Specifically, the patent discloses a programmable controller with modular firmware for communication control, wherein a programmable controller module operably couples a plurality of peripheral devices of various communication disciplines to a data processor or to remote programmable controller modules through a serial interface adapter or parallel interface adaptor. The programmable controller module of Larson et al comprises a special-purpose computer having a program of sub-routines arranged in memory modules, which define and implement specific communication protocols (routines) for different communication disciplines.
However, in contrast to the present invention, the programmable controller of Larson et al does not provide for the connection of the programmable controller to an MP (multi-purpose) bus.
A further arrangement of the prior art is disclosed in U.S. Pat. No. 4,071,887--Daly et al, that patent disclosing an integrated circuit synchronous data adaptor (SSDA) which provides a bi-directional interface for synchronous data interchange. Internal control and interface logic, including a first-in-first-out (FIFO) buffer memory, enables simultaneous transmission and reception of standard synchronous communication characters to allow data transfer between serial data channels and the parallel bi-directional data bus of a bus-organized system.
However, as was the case with respect to the Larson et al patent (discussed above), the Daly et al patent discloses a synchronous controller without mention of the use of a synchronous serial data adaptor with an MP (multi-purpose) bus, as is the case with respect to the present invention.
A third arrangement of the prior art is embodied in a quad serial I/O interface, designated QLVII quad serial I/O interface for DEC LSI-11 based equipment, manufactured by General Robotics Corporation. The subject quad serial I/O interface offers full DEC DLVII-E compatibility on any of four RS-232 ports, and uses one quad-height Q bus module slot. Standard features include auto-answer modem support for BELL-type 103, 113, 202C, 202D and 212 modems. All ports are individually selected to be synchronous serial I/O ports, and baud rates are switch-selectable individually for each port in the range of 50-19,200 baud.
Nevertheless, the QLVII quad serial I/O interface does not support bit-oriented protocols (BOP), as does the present invention. In addition, the QLVII is not software-programmable, configuration information (such as baud rate) being selected by means of manual switches, as opposed to the software selection which typifies the present invention.